Multispectral Impedance Measurements Across Strings Of Interconnected Cells

ABSTRACT

An in-line rapid impedance measurement device and methods of performing in-line rapid impedance spectroscopy including a switch network operable under a switching algorithm useful to rapidly perform targeted impedance measurements to assess state of health, defect or failure of battery packs or modules having a plurality of electrochemical cells interconnected in series or parallel and to isolate individual cells within a pack or module to distinguish between non-repeatable anomalous impedance measurements from repeatable deviant impedance measurements and identify the source of deviant impedance measurements.

This United States Patent application claims the benefit of U.S. Provisional Patent Application No. 62/959,711, filed Jan. 10, 2020, hereby incorporated by reference herein.

I. FIELD OF THE INVENTION

An in-line rapid impedance measurement device and methods of performing in-line fast impedance spectroscopy including a switch network operable under a switching algorithm useful to rapidly perform targeted impedance measurements to assess state of health, defect or failure of battery packs or modules having a plurality of electrochemical cells interconnected in series or parallel and to isolate individual cells within a pack or module to distinguish between non-repeatable anomalous impedance measurements from repeatable deviant impedance measurements and identify the source of deviant impedance measurements.

II. BACKGROUND OF THE INVENTION

A battery is a device including an electrochemical cell having a one positive and one negative terminal which transforms stored chemical energy into electrical energy. Cells can but need not necessarily be assembled into various form factors to provide a required amount of power (“watts” or “W”) and energy (“watt-hours” or “Wh”) for a given application. Battery form factors generally include packs (“P”), modules (“M”) and cells (“C”). A battery module (also referred to as a “module” or “M”) includes a plurality of cells (electrochemical cells (“C”) generally interconnected in series or parallel, or combinations thereof. A battery pack (also referred to as a “pack” or “P”) includes a plurality of modules interconnected in either series (“s”) or parallel (“p”). Interconnecting cells (C), modules (M) or packs (P) in series (s) increases the amount of power (voltage, “V”), while interconnecting cells (C), modules (M), or packs (P) in parallel increases current capacity (“amp-hour” or “mAh”).

Conventional real time battery monitoring (input data is processed within milliseconds for immediate feedback) through a battery management system (“BMS”) typically senses voltage (“V”), current (“I”), or temperature (“T”). Impedance (“Z”) extends the concept of resistance (“Ω”) to alternating current (“AC”) circuits and possesses both magnitude and phase. There is a long felt but unresolved need to integrate near real-time broadband impedance measurements in real time battery monitors or BMS to enhance battery diagnostics. Impedance measurement devices (“IMD”) can perform measurements that can reveal changes in the behavior of electrochemical processes in a cell as a function of age and use which can provide insights into changes in the electrode surface and diffusion layer. See: Kozlowski, J. D. Electrochemical cell prognostics using online impedance measurements and model-based data fusion techniques. 2003. Proceedings from the IEEE Aerospace Conference, Vol. 4. pp. 3257-3270.

III. SUMMARY OF THE INVENTION

Accordingly, a broad object of the invention can be to provide devices and methods to perform AC impedance measurement of a given pack, module or cell form factor at known controlled conditions to establish baseline performance of the battery pack, module, or cell as a function of age and use.

Another broad object of particular embodiments can be to provide i devices and methods to perform a high-fidelity AC impedance measurement of a pack, module or cell at a lower starting frequency range (for example, at about 0.0125 Hz for about 80 seconds or about 0.025 Hz for about 40 seconds). Controlled conditions, can but need not necessarily, include breaks within a charge algorithm after the cells have had a chance to electrochemically and thermally stabilize. Measurements can be performed of a pack, module or of individual cells within the pack or module. Measurements of the pack, module, or cell can, but need not necessarily, be conducted at varying state of charge (“SOC”) conditions during the charge algorithm depending on charge rate (for example, Level 1 charging using a 120 volt connection can take longer than Level 2 charging using a 240 volt connection or Level 3 or extreme fast charging algorithms (“XFC”), so it may be possible to capture more pack, module, or cell measurements). Measurements can be conducted under no-load or load conditions, combinations thereof.

Another broad object of particular embodiments can be to provide devices and methods to perform a mid-fidelity AC impedance measurement of a pack, module, or cell which can be performed at periodic intervals during pack, module or cell use or storage conditions as an indicator of pack, module, or cell status or change of pack, module, or cell status over time (for example pack, module, or cell health or stability). AC impedance measurements of a pack, module, or cell can be performed at a nominal frequency range, depending on cell chemistry (for example, at about 0.1 Hz for about 10 second measurement or at 0.2 Hz for a 5 second measurement). These AC impedance measurements can, but need not, be combined with conventional BMS measurements of V, T, or I of the pack, module or cell which can be used to ascertain SOC, load conditions (under load or not under load), state of use conditions (in use, not in use, or in storage), or the like. Mid-fidelity measurements can be conducted on and entire pack, modules, or cells at periodic intervals. The IMD, the BMS, or remote computer, or combinations thereof, can adjust AC impedance measurement parameters, such as frequency range, excitation level, measurement time period, as needed based on AC impedance data generated during measurement of a battery (for example, if saturation occurs). AC impedance measurements can be conducted under no-load or load conditions, or both.

Another broad object of particular embodiments can be to provide devices and methods to perform a low-fidelity AC impedance measurement of a pack, module, or cell which can, but need not necessarily be performed in a lesser time period than high-fidelity or mid-fidelity AC impedance measurements. Low-fidelity AC impedance measurements of a pack, module, or cell can as an example be performed very fast at about 0.8 Hz for about 1.2 seconds. Low-fidelity AC impedance measurements can, but need not necessarily, be coordinated with high-fidelity or mid-fidelity measurements or with BMS measurements to target different impedance measurement parameters at the pack, module or cell level based on monitored battery conditions or prior impedance measurement data, or combinations thereof. As an illustrative example, one or repeated low fidelity AC impedance measurements of an entire pack, module or individual cells could be triggered by a high-fidelity, mid-fidelity or BMS measurements which deviate from a control or standard threshold measurement values applied to AC impedance test measures of a particular pack, module or cell to distinguish non-repeatable anomalous conditions from repeatable deviant conditions and to identify whether a deviant condition has a comparatively slow or rapid rate of impedance measurement change. AC impedance measurements could be conducted under no-load or load conditions, or combinations thereof.

Another broad object of particular embodiments can be to provide devices and methods which include a switch network operable under a smart switching algorithm to enable drill-down AC impedance measurements using high-fidelity, mid-fidelity or low-fidelity AC impedance measurements, or combinations thereof, to identify a specific pack, module, or cell that may be generating AC impedance measurement which deviates in comparison to the control or standard impedance measurement values for the particular battery type. As an illustrative example, upon detection of an anomalous condition, the IMD, BMS, or remote computer can then trigger a sequence of very rapid, low-fidelity measurements at various subsystems or levels within the pack or module to identify the specific cell string or cell associated with the BMS measurement which deviates from the control or standard impedance measurement value. Whether triggered by the BMS or otherwise, the devices and methods can employ the switch network under control of the switch algorithm which can, but need not necessarily, begin at the pack level and then switch to the module level. Once a module is identified as being associated with the deviant condition, the switch network under control of the switch algorithm can enable low-fidelity AC impedance measurements within the strings of the pack or module. Once the specific string is determined, the switch network would enable low-fidelity AC measurements of the individual cells.

Another broad object of particular embodiments can be to provide devices and methods which perform inline rapid impedance spectroscopy (“iRIS”). iRIS provides rapid, broadband AC impedance measurements of a pack, module or cell using a targeted frequency range. The existing system can measure packs, modules or single cells up to 400 V. Depending on the pack or module assembly, the iRIS sensor can be integrated at any level for near real-time broadband impedance acquisition. This enables advanced diagnostics and prognostics capability. iRIS can provide a significant wealth of information and could be used independently for battery assessment. However, in particular embodiments iRIS can, but need not necessarily, be combined with existing BMS sensor technology (V, T, and I) for battery health and stability assessments.

While this description and the associated figures provide illustrative examples in the context of AC impedance measurements of battery packs, modules, strings of cells, or cells, or battery components, this is not intended to preclude application of embodiments of iRIS, the switch network, or the switching algorithm to measure AC impedance of other devices or objects such as solar panels, solar cells, solar cell components, dielectric materials, or biological systems, components, or objects such human or animal body parts, organs, glands, tissues, membranes, fluids, or isolated biological cells, cell culture growth medium, or to enhance data presentation in electrical impedance tomography.

Additionally, while this description and the associated figures provide illustrative examples of iRIS, this is not intended to preclude embodiments which include or apply the switch network or the switching algorithm to measure AC impedance in batteries, or measure impedance of other devices or objects, using conventional electrical impedance spectroscopy or other impedance measurement techniques, or combinations thereof, embedded in devices which stimulate or excite the battery or object to determine the condition of the device or object including, as examples, impedance noise identification, compensated synchronous detection, or fast summation transformation, or combinations thereof.

Naturally, further objects of the invention are disclosed throughout other areas of the specification, drawings, photographs, and claims.

IV. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a battery impedance plot of real impedance on the X axis versus imaginary impedance on the Y axis and illustrates ohmic resistance value (R_(o)) where the plot crosses the X axis, the charge transfer resistance (Rct) and the low-frequency tail referred to as the Warburg tail (Warburg).

FIG. 2 illustrates a plurality of impedance spectrum as battery impedance plots 16 a . . . 16 j showing change in impedance of a battery over time.

FIG. 3A depicts circuits of an illustrative impedance measurement device and battery management system disposed in a vehicle or other device.

FIG. 3B is an enlargement of the processor and memory depicted in FIG. 3A.

FIG. 3C is an enlargement of the BMS depicted in FIG. 3A.

FIG. 4 is a block diagram of a series cell string (CS_(s)) including a plurality of cells (C1 s, C2 s . . . C_(ns)) electrically connected to a switch network including a plurality of switches (Ss0, Ss1, Ss2 . . . Ss_(n)) switchable to electrically connect one or more of the plurality of cells (C1 s, C2 s . . . C_(ns)) in the series cell string (CSs) to an impedance measurement device and optionally to a load.

FIG. 5 is a block diagram of a parallel cell string (CSp) electrically connected to a switch network including plurality of switches (Sp0, Sp1, Sp2 . . . Sp_(n)) switchable to electrically connect one or more of the plurality of cells (C1 p, C2 p . . . C_(np)) in the parallel cell string (CSp) to an impedance measurement device and optionally to a load.

FIG. 6 illustrates a plurality of cells (C1 ₁, C1 ₂, . . . C1 _(n), C2 ₁, C2 ₂, . . . C2 _(n), C_(N1), C_(N2), . . . C_(Nn)) electrically interconnected in plurality of series cell strings (CSs1, CSs2, CSsn) which can be electrically interconnected in parallel to provide a plurality of parallel cell strings (CSp1, CSp2, CSpn) which can be connected to a switch network including plurality of switches (S) switchable to electrically connect one or more of the cells (C) in a series cell string (CSs1, CSs2, CSsn), or electrically connect the one or more cells in a parallel cell string (CSp1, CSp2, CSpn), or electrically connect all of the plurality of cells (C) interconnected in series and in parallel, to an impedance measurement device and optionally to a load.

FIG. 7 is block flow diagram of an illustrative method of operating an impedance measurement device electrically connected to a switch network switchable under a switch algorithm to target particular impedance measurement parameters to measure impedance of a battery at the pack, module or cell level.

FIG. 8 is a block flow diagram of an illustrative method of performing an impedance measurement of a battery pack, module or cell using a switching algorithm to serially adjust the switches in a switch network to detect impedance measurement anomalies and deviations from preselect impedance measurement thresholds.

FIG. 9A depicts battery impedance measurement plots of real impedance on the X axis versus imaginary impedance on the Y axis obtained by performing a plurality of impedance measurements of three cells electrically interconnected in series cell string (CS_(s)) at high-fidelity impedance measurement and at a mid-fidelity impedance measurement.

FIG. 9B depicts battery impedance measurement plots of a high-fidelity impedance measurement (Controlled Measurement B) across the series string of three cells (CS_(s)) and a subsequent mid-fidelity impedance measurement (In-Use Measurement 4 (IUM 4)) of the series string of three cells (CS_(s)) indicative of an anomalous condition by comparative increase in the impedance of the series string of three cells (CS_(s)).

FIG. 9C depicts battery impedance measurement plots of a high-fidelity impedance measurement (Controlled Measurement B) across the series string of three cells (CS_(s)) and IUM 4 as shown in FIG. 9B, and a subsequent plurality of low-fidelity impedance measurements (Rapid Verification Measurements 1 and 2 (RVM 1 and RVM 2)) of the series string of three cells (CS_(s)) indicative of non-repeatable anomaly condition (IUM 4).

FIG. 9D depicts battery impedance measurement plots of a high-fidelity impedance measurement (Controlled Measurement B) across the series string of three cells (CS_(s)) and IUM 4 as shown in FIG. 9C, and a subsequent plurality of low-fidelity impedance measurements (Rapid Verification Measurements (RVM 3 and RVM 4)) of the series string of three cells indicative of a repeatable deviation from pre-determined impedance measurement threshold values.

FIG. 9E depicts battery impedance measurement plots of low-fidelity impedance measurement of each of Cell 1 (RFDM 1), Cell 2 (RFDM 2), and Cell 3 (RFDM 3) of the series string of three cells (CS_(s)) indicative of failure of Cell 2 in the series string of three cells (CS_(s)).

FIG. 10A depicts battery impedance measurement plots of real impedance on the X axis versus imaginary impedance on the Y axis of four cells electrically interconnected in parallel (CS_(p)) showing that the impedance spectra for Controlled Measurement B has shifted to the right of Controlled Measurement A due to aging of the four cells over a period of time.

FIG. 10B includes battery impedance measurement plots of a high-fidelity impedance measurement Controlled Measurement B across the parallel string of four cells (CS_(p)) as shown in FIG. 10A, and subsequent mid-fidelity impedance measurement In-Use Measurement 4 (IUM 4) of the parallel string of four cells (CS_(p)) indicates an anomalous condition by the substantial comparative increase in the impedance of the parallel string of four cells (CS_(p)).

FIG. 10C depicts battery impedance measurement plots of a high-fidelity impedance measurement Controlled Measurement B across the parallel string of four cells and IUM 4 as shown in FIG. 10B, and a subsequent plurality of low-fidelity impedance measurements Rapid Verification Measurements (RVM 1 and RVM 2) of the parallel string of four cells (CS_(p)) indicative of a non-repeatable anomaly condition (64) IUM 4.

FIG. 10D depicts battery impedance measurement plots of a high-fidelity impedance measurement Controlled Measurement B across the parallel string of four cells (CS_(p)) and IUM 4 as shown in FIG. 10C, and a subsequent plurality of low-fidelity impedance measurements Rapid Verification Measurements (RVM 3 and RVM 4) of the parallel string of four cells (CSp) indicating that In-Use Measurement 4 was a repeatable a deviant condition.

FIG. 10E depicts battery impedance measurement plots of low-fidelity impedance measurements Rapid Failure Detection Measurements of each of Cell 1 (RFDM 1), Cell 2 (RFDM 2), Cell 3 (RFDM 3) and Cell 4 (RFDM) of the parallel string of fours cells (CS_(p)) indicative of failure of Cell 1 in the parallel string of four cells (CS_(p)).

FIG. 11A depict battery impedance plots of mid-fidelity impedance measurements of a cell under load conditions and under no load conditions at a starting frequency of about 0.1 Hz which show that the impedance measurements of the cell (C) under load conditions and under no-load conditions are similar.

FIG. 11B depict battery impedance plots of mid-fidelity impedance measurements of a cell under load conditions and under no load conditions at a starting frequency of about 0.3 Hz which show that the impedance measurements of the cell (C) under load conditions and under no-load conditions are similar.

FIG. 11C depict battery impedance plots of mid-fidelity impedance measurements of a cell under load conditions and under no load conditions at a starting frequency of about 0.8 Hz which show that the impedance measurements of the cell (C) under load conditions and under no-load conditions are similar.

FIG. 12 depicts a battery impedance measurement plots of mid-fidelity impedance measurements of four cells electrically connected in series (CS_(s)) having one cell within the string subjected to a discharge condition under load conditions and under no load conditions at a starting frequency of about 0.1 Hz.

V. DETAILED DESCRIPTION OF THE INVENTION

Now with general reference to FIGS. 1 through 12 which provide illustrative examples of IMD (1) and iRIS (1′) and methods for using impedance measurement devices (1)(1′) for performing impedance measurements (2) on illustrative electrical circuits (3) including a battery (4) having a plurality of cells (cell 1, cell 2 . . . cell_(n))(also referred to as C1, C2, . . . C_(n)) whether electrically interconnected in a series circuit (5) where the current through each of the components in the series circuit (5) is the same, and the voltage across the series circuit (5) is the sum of the voltages across each component, or in a parallel circuit (6) where the voltage across each of the components in the parallel circuit (6) is the same, and the total current is the sum of the currents flowing through each component, or combinations thereof.

In particular embodiments, the electrical circuit (3) can, but need not necessarily, include a load (7) consuming electrical power from the plurality of cells (C_(n)). In particular embodiments, the electrical circuit (3) may include a switch network (8) including a plurality of switches (9) (switch 1, switch 2 . . . switch_(n))(also referred to as S1, S2 . . . S_(n)) which allows performance of impedance measurements (2) on all of the plurality of cells (C_(n)) in the electrical circuit (3), performance of impedance measurements (2) on a cell string (CS), or on each cell (C1, C2, . . . C_(n)) of the plurality of cells (C_(n)) independent of the other cells (C1, C2, . . . C_(n)) in a plurality of cells (C_(n)) in the electrical circuit (3). While particular illustrative examples include an IMD (1) comprising an inline rapid impedance spectroscopy device (“iRIS device” or “iRIS”)(1′) and methods of using an iRIS device (1′), this is not intended to preclude embodiments including or substituting other types or kinds of IMD (1) capable of generating a stimulus signal (10) to one or more cells (C1, C2, . . . C_(n)) within a plurality of cells (Ce) of a battery (4) which can, but need not necessarily, be configured as a module (“M”) or pack (“P”), detecting a response signal (11) from one cell (C) or more cells (C1, C2, . . . C_(n)) within a plurality of cells (C_(n)), and estimating the impedance (12) of the one cell (C) or more cells (C1, C2, . . . C_(n)) within a plurality of cells (C_(n)).

Elements, circuits, modules, and functions may be shown in block diagram form. Moreover, specific implementations shown and described are illustrative only and should not be construed as the only way to implement the present disclosure unless specified otherwise herein. Additionally, block definitions and partitioning of logic between various blocks is illustrative of a specific implementation. However, the present disclosure may be practiced by numerous other partitioning solutions. For the most part, details concerning timing considerations and the like have been omitted where such details are not necessary to obtain a complete understanding of the present disclosure by persons of ordinary skill in the relevant art.

Those of ordinary skill would appreciate that the various illustrative logical blocks, modules, circuits, and algorithm described in connection with embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and acts are described generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments described herein.

When implemented with hardware, the embodiments disclosed herein may be implemented or performed with a general purpose processor, a special purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. When executing software for carrying out processes for embodiments described herein, a general-purpose processor should be considered a special-purpose processor configured for carrying out such processes. A processor may also be implemented as a combination of computing devices, such as, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

In addition, it is noted that the embodiments may be described in terms of a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operational acts as a sequential process, many of these acts can be performed in another sequence, in parallel, or substantially concurrently. In addition, the order of the acts may be re-arranged. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, or a step depending on the application. Furthermore, the methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.

It should be understood that any reference to an element herein using a designation such as “first,” “second,” and so forth does not limit the quantity or order of those elements, unless such limitation is explicitly stated. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements may be employed or that the first element must precede the second element in some manner. In addition, unless stated otherwise, a set of elements may comprise one or more elements.

Electrochemical Impedance Spectroscopy. Electrical Impedance Spectroscopy (EIS) measurements involve measuring a response signal (11) to a stimulus signal (10). This stimulus signal (10) can be either a current stimulus signal (10 a) or a voltage stimulus signal (10 b) with the response signal (11) measure being the complement (for example, if the stimulus signal (10) is a sum of sines (SOS) root mean square (RMS) current stimulus signal (10 a) (SOS RMS current) then the response is a voltage response signal (11 a), if the stimulus signal (10) is a voltage stimulus signal (10 b) then the response signal (11) is a current response signal (11 b)). Data processing then calculates the complex impedance (12) of the cell (4) at the stimulus signal frequency (13). This process is generally performed at each of a plurality of frequencies (13 a, 13 b, 13 c, 13 d . . . ) to create an array of the complex impedances (12). Conventional use of EIS produces impedance measurements (14) that typically have a range from about 100 kHz to about 10 mHz may take an amount of time in the range of about ten minutes to about an hour to perform depending on impedance measurement parameters (31). By comparison iRIS devices (1′) produce impedance measurements (14) from about 2 kHz to about 10 mHz and may take an amount of time in the range of about 1 sec to about 80 sec depending on the impedance measurement parameters (31). As illustrative examples, iRIS devices (1′) can perform impedance measurements (14) from about 1.6 kHz to about 12 mHz in about 80 sec, from about 1.6 kHz to about 0.1 Hz in about 10 sec, or from about 1.6 kHz to about 0.8 Hz in about 1.2 sec, or increments between a start frequency (50) of about 1.6 kHz to about 12 mHz; although this is not intended to preclude certain embodiments including or using conventional EIS IMD (1).

In particular embodiments, the iRIS device or sensor can provide additional metrics for enhanced in-situ (and ex-situ) battery state-of-health (SOH) and state-of-stability (SOS) assessments. It can inject an excitation signal consisting of a sum of sinusoids over a broad frequency range with one period of the lowest frequency and captures the battery response. Particular embodiments of the iRIS sensor are capable of measuring batteries up to 50V having impedances down to 3 mW with 0.1 mW resolution. The measurable battery impedance can be lowered to approximately 1 mW with 0.04 mW resolution if the maximum iRIS upper voltage threshold is reduced to 10V. However, studies have shown that there is a long felt unresolved need to ensure accurate and repeatable measurements during SOH and SOS assessments (especially for subtle initial changes in battery characteristics that can indicate the onset of degradation/failure).

Thus, the iRIS system including hardware and software have been developed for higher resolution capability with improved signal-to-noise ratios and measurement repeatability. These enhancements enable higher levels of detectability in both SOH and SOS as a function of battery aging and use. Results show that a cell-level iRIS' system (<5V) can now achieve a resolution of 4.8 mW; a 10-V system (for example, cell strings and sub-modules) can now achieve a resolution of 10.5 mW. Another advantage of these upgrades is the ability to measure lower-impedance batteries. Measurements have been conducted on test circuits, which include an RC network intended to simulate battery characteristics.

Pack, Module or Cell Impedance Plots.

Now with primary reference to FIG. 1, an impedance spectrum (15) is typically displayed graphically as a plot (16) similar to a standard Nyquist plot. Following convention among electrochemical researchers, these plots differ in that a negative imaginary impedance in ohms (17)(also referred to as “imaginary impedance”) is plotted on the Y axis (and only positive impedance in ohms (18) (also referred to as “real impedance”) of each of a plurality of stimulus signal frequencies (13) is plotted on the X axis. The ohmic resistance value (R_(o)) is the real impedance value where the plot crosses the X axis (in the example of FIG. 1, the ohmic resistance is about 251.2 Hz). The mid-frequency semicircle is the charge transfer resistance (Rct) and the low-frequency tail is often referred to as the Warburg tail (“Warburg”).

Now with primary reference to FIG. 2, which displays a plurality of impedance spectrum (15) as battery impedance plots (16 a . . . 16 j) showing change in impedance of a battery (4) over time. Plot (16 a) illustrates a baseline impedance measurement (14) of the battery (4). Plots (16 b . . . 16 d) illustrate impedance measurements (14) of the battery (4) upon elapse of 12, 24, and 36 weeks, respectively. Plots (16 e . . . 16 g) illustrate impedance measurements of the battery (4) upon elapse of 48, 60, and 72 weeks, respectively. Plots (16 h . . . 16 j) illustrate impedance measurements of the battery (4) upon elapse of 84, 96, and 108 weeks, respectively. The semicircles within the plots, corresponding to Rct or the R_(o), or combinations thereof, can increase as the cell ages and can thus be used to effectively estimate the battery SOH by analyzing movement of the Rct within the plots (16 b . . . 16 j) over time.

Impedance Measurement Device. Now, with general reference to FIG. 3 which depicts circuits of an illustrative IMD (1), which can, but need not necessarily, be an iRIS device (1′), including a processor (19) in communication with a non-transitory computer readable medium (20) containing a program code (21) which implements one or more impedance spectrum algorithms (22), a sum of sines generator (“SOSG”)(23); a data acquisition system (“DAS”)(24); a preamplifier (25), a connection safety circuit (26) and a power supply (27). Auto calibration (28) may be included in some embodiments under control of the processor (19); although in certain embodiments, calibration can be performed as described in U.S. Pat. No. 10,436,873, hereby incorporated by reference herein. An illustrative impedance measurement device (1) suitable for use in particular embodiments can be made and used as described in U.S. Pat. No. 10,379,168, hereby incorporated by reference herein.

Examples of impedance spectrum algorithms (22) useful to process AC impedance measurement response time record (29) to determine impedance (12) as a function of the stimulus signal frequencies (13) utilized in the stimulus signal (10) to the battery (4) include, but are not limited to, harmonic compensated synchronous detection (HCSD), fast summation transformation (FST), generalized fast summation transformation (GFST), frequency cross talk compensation (FCTC), time cross talk compensation (TCTC), harmonic orthogonal synchronous transformation (HOST). See, for example, U.S. Pat. Nos. 7,688,036; 7,395,163 B1; 7,675,293 B2; 8,150,643 B1; 8,352,204 B2; 8,762,109 B2; 8,868,363 B2; and 9,244,130 B2, and United States Patent Publications Nos. 2011/0270559 A1; 2014/0358462 A1; and 2017/0003354 A1 (each hereby incorporated by reference herein) which describe the implementation of one more of the spectrum algorithms (22).

The IMD (1) can, but need not necessarily, include a remote computer (30)(or the computer may be local or integral to the IMD (1)) via a Universal Serial Bus (USB) interface or other suitable interface, such as, for example, hardwire serial interfaces, hardwire parallel interfaces, and wireless interfaces (as examples, WI-FI®, ZIGBEE®, BLUETOOTH®). In particular embodiments, the remote computer (30) can include all or part of the components necessary to control the 1 MB (1) to perform impedance measurements (14) (as shown in the examples of FIGS. 7 and 8) of the battery (4).

The processor (19) (whether integral to the IMD (1) or included in the remote computer (30)) can synchronize and control the DAS (24), the SOSG (23) and the preamplifier (25) in accordance with control impedance measurement parameters (31) and generate impedance measurement commands (32) to operate the IMD (1) dictated by the program code (21). In particular embodiments, the processor (19) can interface with the remote computer (30) to download desired impedance measurement parameters (31) and impedance measurement commands (32) and upload various impedance measurement data (33). As non-limiting examples, the processor (19) or memory (20), can include adequate buffer memory (34) to hold an acquired battery impedance measurement time record (29) until processed, hold the desired number of high-fidelity, mid-fidelity, or low fidelity battery impedance spectrum algorithms (22 a, 22 b, 22 c, respectively) and the corresponding high-fidelity, mid-fidelity, or low-fidelity resolution SOS samples (22 a′, 22 b′, 22 c′).

The processor (19) may be configured to accept downloaded impedance measurement commands (32) and impedance measurement parameters (31) and upload to the remote computer (30) archived battery impedance measurement data (33) under direction of the remote computer (30). Additionally, the IMD (1) may be able to be controlled via human interaction in a user interface (“GUI”) on the remote computer (30) or the IMD (1) for the purpose of inputting impedance measurement commands (32) and impedance measurement parameters (31) to the 1 MB (1).

When an impedance measurement (2) or targeted impedance measurement (14) of a pack (P), module (M) or cell (C) under test is triggered, the DAS (24) can send out a power up signal (35) to a power supply (27) relay to power up a DC voltage amplifier (25) and a connection safety circuit (26). The DC battery voltage (36) may be measured by a battery response amplifier (37) and input to the DAS (24) as the battery voltage analog signal (38) of the DC battery voltage (36). The DAS (24) or the processor (19) may digitize the battery voltage analog signal (38) of the DC battery voltage (36) and may send the digitized result to the remote computer (30).

When the stimulus signal (10), and in particular embodiments the SOS current (41) stimulates a battery (4) under test, the measured response signal (11) at its terminals includes the DC battery voltage (36) plus a SOS voltage response (42) of the SOS current (41) acting on the internal impedance of the battery (4). It is this SOS voltage response (42) that, when captured and processed, yields the impedance spectrum (15) of the measured battery response signal (11). To accurately detect the SOS voltage response (42), the DC battery voltage (36) can be subtracted out prior to measuring the SOS voltage response (42) allowing an analog to digital convertor (43) to focus on the desired response signal (11) which can substantially improve accuracy. This subtraction of the DC battery voltage (36) may be accomplished by measuring the DC battery voltage (36) prior to the application of the stimulus signal (11) (for example an SOS current (41)) to the battery (4) under test and then feeding back a computer generated buck voltage signal (44) to generate a buck bias voltage (39) by the battery response amplifier (37) from the total of the DC battery voltage (36) and the SOS voltage response (42) to yield only the corresponding response signal (11) (for example an SOS voltage (42)).

The remote computer (30) or the processor (19) can send a connection signal (46) to the connection safety circuit (26) to connect the battery (4) to current drivers (48) in the DC voltage amplifier (25). With the DC voltage amplifier (25) connected to the battery (4), the remote computer (30) or processor (19) sends a battery impedance measurement signal (10′) such as, an SOS signal (41′), or other suitable measurement signal (10′) to the DC voltage amplifier (25).

The impedance measurement signal (10′) may be smoothed out using a smoothing filter (47), then fed into a current driver (48), which converts the signal into the stimulus signal (10), such as an SOS current (41). The battery response amplifier (37) in the DC voltage amplifier (25) detects the DC battery voltage (39) and subtracts the buck bias voltage (39) to become the battery response signal (11) that may be digitized by the DAS (24). The captured impedance measurement time record (29) may be processed using one or more of the spectrum algorithms (22) discussed herein to generate the impedance spectrum (15) which can be converted to impedance plots (16).

As an illustrative example, the IMD (1) can process a battery impedance spectrum (15) with at least fifteen frequencies of resolution for FST and eleven frequencies for GFST (based upon triads) or HCSD, when the start frequency is 0.1 Hz. In addition, the IMD (1) can support a dither feature (49) of high spectrum resolution with dither steps as fine as 21/4 for FST and 31/4 for GFST based upon triads. For suitable results, the captured impedance measurement time record (29) may be as low as one period of the lowest frequency and the IMD (1) may be able to process an impedance measurement time record (29) with a start frequency (50) of as low as 2 kHz or a stop frequency (51) as high as 10 kHz; however, these illustrative examples are not intended to obviate embodiments which can have a lower start frequency or a higher stop frequency.

The SOSG (23) can, under control of the processor (19) or remote computer (30), generate a zero-order hold synthesis of the SOS as an input to the DC voltage amplifier (25). As a non-limiting example, a sample rate for the SOSG digital to analog convertor (43) may be configured at least one-hundred times the highest stimulus signal frequency (13) and compatible with the smoothing filter (47) within the DC voltage amplifier (25).

In one embodiment, the SOSG (23) under control of the processor (19) can synthesize a sample clock (52) to be used by the DAS (24). FST requires a sampling frequency that is octave harmonic with the highest frequency of the SOS stimulus and is at least 4 times higher. GFST based on triads requires a sampling frequency that is triad harmonic with the highest frequency of the SOS stimulus and is at least 9 times higher. The SOSG (23) can include a programmable signal level for the DAC output to the smoothing filter (47), which enables the processor (19) to control the level of the SOS RMS current (41) to the battery (4) under test.

The DAS (23) may be configured with 16 bits of resolution and accept an external sample clock (52) from the SOSG (23). The DAS (23) may accept an enable signal from the processor (19) to start acquiring data concurrent with the application of the stimulus signal (10), such as the SOS current signal (41) to the battery (4) under test. The DAS (23) can accept the analog battery voltage signal (38) that has been conditioned by the DC voltage amplifier (25) for digitizing. The DAS (23) may include a buffer memory to hold a sample of the digitized battery voltage signal (38) for uploading to memory (20). Each of the acquired samples may become part of the time record (29) that is input into the spectrum algorithms (22), such as an FST algorithm. Additionally, the DAS (23) may acquire a measurement of the DC battery voltage (V), battery temperature (T) and battery current (I) of the battery (4), whether by the IMD (1) or via the BMS (53) which may be prior to the application of the stimulus signal (10), such as the SOS current (41). When a stimulus signal (10), such as the SOS current (41) is not being sent to the battery (4) under test, the connection to that battery (4) can be disconnected via operation of the safety circuit (26) or one or more switches in the switch network (8).

The DC voltage amplifier (25) input signal may be the zero-order hold impedance measurement signal (10′), such as an SOS signal from the SOSG (23). The DC voltage amplifier (25) may include an active Butterworth low pass filter as the smoothing filter (47) and include about 1 db of attenuation at 8 kHz and 60 db of attenuation to the frequencies introduced by the zero-order hold upon the impedance measurement signal (10′). Additionally, the BMS (53) can provide V, T, I analog or digital data to the DAS (24). All grounds in the DC voltage amplifier (25) may be brought to a single point chassis ground of an object or vehicle (54) which may contain the battery (4) or IMD (1), iRIS device (1′) or BMS (53), or combinations thereof.

The impedance spectrum (15) generated during an impedance measurement (14) of a battery (4) can be passed to the processor (19) or the remote computer (30) in any suitable format (as an illustrative example: Comma Separated Values (CSV) format). Each individual impedance spectrum (15) may further include one or more of: a time stamp (55), an information header (56), the stimulus signal frequencies (13), the real impedance (18), the imaginary impedance (17) and the DC battery voltage (36) for the impedance spectrum (15), SOS RMS current (41); the magnitude and phase calibration constants (57).

In-line Rapid Impedance Spectroscopy (iRIS®). Again, with primary reference to FIG. 3, particular embodiments of the IMD (1) or iRIS device (1′) can measure the impedance spectrum (15) of a battery (4), other energy storage device, or other device, or component, under test in one second or less. An iRIS device (1′) can be configured to measure all of the component stimulus signal frequencies (13) of a stimulus signal (11), such as an SOS current (41), in parallel within one period of the lowest frequency (22 c). In one embodiment, the iRIS device (1′) can process a battery impedance spectrum (15) with at least 15 frequencies (13) of resolution for FST and 11 frequencies for GFST (based upon triads) when the start frequency (50) comprises about 0.1 Hz. In addition, the iRIS device (1′) may be able to support a dither feature of high spectrum resolution with dither steps as fine as 21/4 for FST and 31/4 for GFST based upon triads. The impedance measurement time record (29) can, but need not necessarily, comprise one period of the lowest frequency (13 a) and the IMD (1), or iRIS device (1′) can, but need not necessarily, process a response signal (11), such as an SOS voltage (45) with a start frequency (50) of as low as about 10 mHz or a stop frequency (51) as high as about 10 kHz, as above described.

High-Fidelity AC Impedance Measurement. In particular embodiments, impedance measurements (14) used as diagnostic sensor in or with a BMS (53) can be performed on a pack (P), module (M) or individual cell (C) with high-fidelity impedance measurements (14 a) to establish reference measurement (such as reference measurement 16 a in the example of FIG. 2) of the pack (P), module (M), or cell (C) as a function of age or use, or combinations thereof. Battery controlled conditions (4 c) can include breaks within a battery charge algorithm (58) after the battery (4)(P)(M)(C) has had a chance to electrochemically or thermally stabilize or during extended rest intervals after a discharge. As illustrative examples, impedance measurement (14) of pack (P), module (M), or cell (C) at high-fidelity (14 a) can be conducted at stimulus frequencies (13) starting at about 0.0125 Hz for an 80 second (“sec”) measurement or 0.025 Hz for a 40 sec measurement using 18 frequencies within the stimulus signal (10) up to 1638.4 Hz. Impedance measurement of a pack (P), module (M), or cell (C) can be conducted at varying SOC conditions (4 e) during the charge algorithm (58) depending on a battery charge rate (59) (as illustrative examples: Level 1 charging (59 a) may take longer than Level 2 charging (59 b) or Level 3 charging (59 c) or extremely fast charging (“XFC”)(59 d). High-fidelity impedance measurements (14 a) can be conducted under battery no-load conditions (7 a) or battery load conditions (7 b), or combinations thereof. High-fidelity impedance measurements (14 b) can, but need not necessarily, be combined with V, T, I measurements of the pack (P), module (M), or cell (C) to ascertain SOC (4 d), battery load condition (14 b), or other conditions of the pack (P), module (M) or cell (C). In particular embodiments, the IMD (1)(a′), remote computer (30) or the BMS (53) may also adjust impedance measurement parameters (31) such as stimulus signal frequencies (13), stimulus signal amplitude (60), impedance measurement fidelity (14 a . . . 14 c), impedance measurement time period (61), impedance measurement decimation (62) based on impedance measurements (14), such as detected saturation of the analog to digital converter (43).

Mid-Fidelity AC Impedance Measurement. Again, with primary reference to FIG. 3, in particular embodiments, impedance measurements (14) used as a diagnostic sensor in or with a BMS (53) can be performed on a pack (P), module (M) or individual cell (C) at mid-fidelity impedance measurements (14 b) at periodic intervals during pack (P), module (M), or individual cell (C) battery use conditions (4 a) or battery storage conditions (4 b). As illustrative examples, AC impedance measurement of the pack (P), module (M), or individual cell (C) can be conducted at a start frequency of about 0.1 Hz for a 10 sec measurement or at about 0.2 Hz for a 5 sec measurement using 15 frequencies with the stimulus signal (10) up to 1638.4 Hz. Mid-fidelity impedance measurements (14 b) may be conducted under battery no-load conditions (4 a) or battery load conditions (4 b), or combinations thereof. Mid-fidelity impedance measurements (14 b) can, but need not necessarily, be combined with V, T, I measurements of the pack (P), module (M), or cell (C) to ascertain SOC (4 d), battery load condition (14 b), or other conditions of the pack (P), module (M) or cell (C). In particular embodiments, the IMD (1)(a′), remote computer (30) or the BMS (53) may also adjust impedance measurement parameters (31) such as stimulus signal frequencies (13), stimulus signal amplitude (60), impedance measurement fidelity (14 a . . . 14 c), impedance measurement time period (61), impedance measurement decimation (62) based on impedance measurements (14), such as detected saturation of the analog to digital converter (43).

Low-Fidelity AC Impedance Measurement. Again, with primary reference to FIG. 3, in particular embodiments, impedance measurements (14) used as a diagnostic sensor in or with a BMS (53) can be performed on a pack (P), module (M) or individual cell (C) at low-fidelity impedance measurements (14 c) at periodic intervals during pack (P), module (M), or individual cell (C) during battery use (4 a) or battery storage conditions (4 b). Low-fidelity impedance measurement (14 c) can be conducted in a lesser amount of time compared to high-fidelity or mid-fidelity impedance measurements (14 a)(14 b). Very fast low-fidelity impedance measurements (14 c) can be used to further characterize pack (P), module (M) or individual cell (C) condition when an AC impedance measurement (14) occurs outside pre-determined impedance measurement threshold value(s) (63). As illustrative examples, upon identification of an impedance measurement (14) which occurs outside of pre-determined impedance measurement threshold value(s) (63) the processor (19), the remote computer (30) or the BMS (53) can trigger a sequence of very fast low fidelity impedance measurements (14 c), such as, impedance measurements (14) starting at about 0.8 Hz for about 1.2 sec for 11 frequencies up to 1638.4 Hz. The very fast low-fidelity impedance measurements (14 c) can be used to further diagnose or characterize the pack (P), module (M) or cell (C) condition. In a first instance, the low-fidelity impedance measurements (14 c) can be repeated to establish whether the prior impedance measurement (14) was an anomalous non-repeatable variation from the prior impedance measurement (14) (also referred to as an “anomaly condition”)(64) or repeatable variation from the prior impedance measurement (14) (also referred to as “a deviant condition”)(65). If not an anomalous condition (64), then repeated very fast low impedance measurements (14 c) can be used to deduce the impedance rate of change (66) in the deviant condition (65) of the pack (P), module (M), or cell (C). The impedance change rate (66) in the impedance measurement (14) can be compared to pre-determined impedance change rate threshold value(s) (67), and if the impedance change rate (66) exceeds the pre-determined impedance change rate threshold value(s) (67), the processor (19), remote computer (30) or BMS (53) can trigger activation of a warning indicator (68) (whether visual, auditory, tactile, or a combination thereof) to service or abandon the battery (4), object, device or vehicle (54) in which the pack (P), module (M) or cell (C) resides.

Switch Network. Again, with primary reference to FIG. 3, in particular embodiments, a string of cells or cell string (“CS”) electrically connected in series (CSs) or parallel (CSp) can be electrically connected to a switching circuit (8) (also referred to as “a switch network”) including plurality of switches (S0, S1, S2 . . . S_(n)) switchable to electrically connect one or more of the cells (C1, C2, . . . C_(n)) in a series string of cells (C1 s, C2 s, . . . C_(ns)), or electrically connect the one or more cells (C1, C2, . . . C_(n)) in a parallel string of cells (C1 p, C2 p, . . . C_(np)), or electrically connect all of the plurality of cells (C1, C2, . . . C_(n)) interconnected in series (s) and/or in parallel (p), to an IMD (1), and in particular embodiments an iRIS device (1′). The switch network (8) can be operated under control of a smart switching algorithm (70) of the program code (21) to target impedance measurements (14) at the level of the pack (P) or module (M) and then at the level of the cell (C) to rapidly determine the source of impedance measurement(s) (14) which deviate in comparison with pre-determined impedance measurement threshold value(s) (63) or pre-determined impedance measurement change rate value(s) (67).

Switching Algorithm. A switching algorithm (70) (also referred to as the “SA”) under control of the, processor (19), remote computer (3), or the BMS (53) can generate a switch signal (70′) to initiate and enable drill-down impedance measurements (14) using high-fidelity (14 a), mid-fidelity impedance measurements (14 b) or low-fidelity impedance measurements (14 c) to identify a specific pack (P), module (M), or cell string (CS) or cell (C) associated with a response signal that falls outside of the pre-determined impedance measurement threshold value(s) (63). In particular embodiments, the switch algorithm (70) can, but need not necessarily, initiate impedance measurement (14) at the pack (P) or module (M) level and then switch to impedance measurement of individual cells (C). Once the specific pack (P) or module (M) associated with impedance measurement (14) exhibiting a deviant condition (65) is identified, the switching algorithm (70) enables fast low fidelity impedance measurements (14 c) of strings of cells (Cs) within the pack (P) or module (M). Once the specific string of cells (CS) associated with the deviant impedance measurement (14) is identified, then the switching algorithm (70) enables fast low-fidelity impedance measurements (14 c) of the individual cells (C) within the cell string (CS).

In particular embodiments, the SA (70) can be executed to conduct high-fidelity impedance measurements (14 a) of the pack (P), module (M), or individual cells (C) under controlled impedance measurement conditions (4 c) to evaluate pack (P), module (M) or cell (C) SOH (4 e). Controlled impedance measurement conditions (4 c) means a known, and preferably consistent, test cell configuration (pack, module, cell string or cell) and test cell conditions (V, I, T, SOC or other conditions); however, not necessarily in real time. As an illustrative example, this could be implemented as part of a BMS charge algorithm (58).

The SA (70) can then be executed to conduct near real-time impedance measurements (14) of the same test cell configuration (pack, module, cell string or cell) whether the object or device (54) containing the pack (P), module (M) or cell (C) is in a use condition (4 a) or in a rest condition (4 b) or combinations thereof. Impedance measurements (14) conducted under no-load conditions (7 a) and load conditions (7 b), as needed, to diagnose battery (4) SOC (4 d), SOH (4 e), stability (4 f), or similar conditions, or combinations thereof. These impedance measurements (14) can be used to adjust power supply (27) management and battery use conditions (4 a) and can estimate remaining run time based on battery use conditions (4 a).

In the event the impedance measurements (14) in comparison with pre-determined impedance measurement threshold value(s) (63) deviate from the pre-determined impedance measurement threshold value(s) (63), the SA (70) can be executed to trigger real time low-fidelity impedance measurements (14 a) to determine if the impedance measurement (14) comprises an anomalous condition (64) or a deviant condition (65). If determined to be a deviant condition (65), the SA (70) can trigger additional impedance measurements (14) of each cell string (CS) within a pack (P) to identify the cell string (CS) associated with the deviant condition (65). Upon determination of the cell string (CS) associated with the deviant condition (65), then the SA (70) can trigger impedance measurements (14) of each cell (C) within the cell string (CS) associated with the deviant condition (65). Once the cell (C) associated with the deviant condition (65) is identified the SA (70) can trigger repeated impedance measurements (14) of the cell (C) associated with the deviant condition (65), to determine the impedance measurement rate of change (66) of the deviant condition (65). If the deviant condition (65) or the impedance measurement rate of change (66) of the deviant condition (65) exceeds corresponding pre-determined impedance measurement threshold value(s) (63) or pre-determined impedance measurement change rate threshold value(s) (67), the SA (70) can be executed to trigger warning indicators (68) associated with the detected deviant condition (65) or impedance measurement change rate (66) of the deviant condition (65).

Impedance Measurement of Series String of Cells. Now, with primary reference to FIG. 4, which illustrates a cell string (CS) electrically interconnected in a series (CSs) where the current through each of the components in the series circuit (5) is the same, and the voltage across the series circuit (5) is the sum of the voltages across each component. The series cell string (CSs) includes a plurality of cells (C1 s, C2 s . . . C_(ns)) electrically connected to a switch network (8) including plurality of switches (Ss0, Ss1, Ss2 . . . Ss_(n)) switchable to electrically connect one or more of the plurality of cells (C1 s, C2 s . . . C_(ns)) in the series cell string (CSs) to an IMD (1) or iRIS device (1′).

In the illustrative example of FIG. 4, closing switches Ss0 and Ssn and opening Ss1 and Ss2 enables impedance measurements (14) of the entire series cell string (CSs). One or more plurality of cells (C1 s, C2 s . . . C_(ns)) in the series cell string (CSs) can be isolated for impedance measurement (14) by closing or opening certain of the plurality of Ss. As one example, closing switches Ss1 and Ss2 while opening Ss0 and Ssn allows impedance measurement (14) of only C2 s in the plurality of cells (C1 s, C2 s . . . C_(ns)).

In particular embodiments, C1 s, C2 s . . . C_(ns) may each comprise a pack (P), a module (M), or an individual cell (C) connected in series (CSs) in a battery (4). In an embodiment where cell C1 s is a module (M) or sub-module, rather than an individual cell in a series string, a similar switching circuit (8) can be employed with the module (M) or sub-module to allow impedance measurement (14) of a series string of modules or sub-modules with impedance measurement (14) of one or more individual cells (C). The IMD (1)(1′) and associated hardware can be configured to operate under the maximum voltage across the series string of cells (CS). In particular embodiments, a load (7) can be electrically connected to the series string of cells (CS) to provide power to the load (7). IMD (1)(1′) measurements of the series string of cell (CS), or one or more cells (C) within the series string of cells (CS), can be conducted by operation of the switch circuit (8) without interrupting power to the load (7).

Impedance Measurement of Parallel String of Cells. Now, with primary reference to FIG. 5, which illustrates a parallel cell string (CSp) including plurality of cells (C1 p, C2 p . . . C_(np)) electrically interconnected in a parallel where the voltage across each of the components is the same, and the total current is the sum of the currents flowing through each component in the parallel circuit. The parallel string of cells (CSp) can be electrically connected to a switching circuit (8) including plurality of switches (Sp0, Sp1, Sp2 . . . Sp_(n)) switchable to electrically connect one or more of the plurality of cells (C1 p, C2 p . . . C_(np)) in the parallel cell string (CSp) to an IMD (1) or iRIS device (1′).

In the illustrative example of FIG. 5, closing all the switches Sp0 . . . Sp_(n) enables impedance measurements (14) of the entire parallel string of cells (CSp). One or of the plurality of cells C1 p, C2 p . . . C_(np)) in the parallel cell string (CSp) can be isolated for impedance measurement (14) by closing or opening certain of the plurality of switches (Sp0, Sp1, Sp2 . . . Sp_(n)). As one example, closing switches Sp0 and Sp2 while opening Sp1 and Spn provides access directly to C2 p in the parallel string of cells (CSp). The IMD (1) and associated hardware can be configured to operate under the maximum voltage across the parallel string of cells (CSp). In particular embodiments, a load (7) can be electrically connected to the parallel string of cells (CSp) to provide power to the load (7). Impedance measurements (14) of the parallel cell string (CSp), or one or more cells (C) within the parallel string of cells, cannot be conducted by operation of the switch circuit (8) without temporarily switchably isolating the cell (C) under test from the load (7) provided that the load (7) can be supported by temporary reduction in current.

Impedance Measurement of Series and Parallel String of Cells. Now, with primary reference to FIG. 6, which illustrates a plurality of cells (C1 ₁, C1 ₂, . . . C1 _(n), C2 ₁, C2 ₂, . . . C2 _(n), C_(N1), C_(N2), . . . C_(Nn)) electrically interconnected in plurality of series cell strings (CSs1, CSs2, CSsn) and the plurality of series cell strings (CSs1, CSs2, CSsn) can be electrically interconnected in parallel to provide a plurality of parallel cell strings (CSp1, CSp2, CSpn) where the current through each of the components in a series circuit is the same, and the voltage across the series circuit is the sum of the voltages across each component and where each of the voltage across each of the components in the a parallel circuit is the same, and the total current is the sum of the currents flowing through each component in the parallel circuit. The string of cells connected in series and parallel can be electrically connected to a switching circuit (8) including plurality of switches (S) switchable to electrically connect one or more of the cells (C) in a series cell string (CSs1, CSs2, CSsn), or electrically connect the one or more cells in a parallel cell string (CSp1, CSp2, CSpn), or electrically connect all of the plurality of cells (C) interconnected in series and in parallel, to an IMD (1) or iRIS device (1′).

In the illustrative example of FIG. 6, closing all the switches except S01, S02, S11, S12, Sn1, and Sn2 enables impedance measurements (14) across the entire plurality of cells electrically interconnected in series or in parallel. Alternatively, an entire series cell string (CSs1, CSs2, CSsn) can be measured by an IMD (1)(1′). For example, series cell string CSs2 can be measured by closing switches S00, S10, Sb1, Sb2, Sbn, S1 n, and S0 n and leaving the remaining switches open. Similarly, an entire parallel cell string (CSp1, CSp2, CSpn) electrically interconnected in parallel can be measured by an IMD (1). For example, parallel cell string (CSp2) the second row of cells electrically interconnected in parallel (C21, C22, and C2 n) could be measured by an 1 MB (1)(1′) by closing switches S01, Sa2, S11, Sb2, Sn1, Sm2, Sn2, S12, and S02. Similarly, other combinations of strings or cells whether electrically interconnected in series and/or parallel can be measured by various combinations of open and closed switches in the switching algorithm (70). Measurement of individual cells by an IMD (1)(1′) can also be achieved. For example, closing switches S01, S11, Sb2, S12, and S02 while opening all the other switches provides isolated impedance measurement (14) of C22 in the system. Accordingly, the switching algorithm (70) can enable impedance measurement at the pack (P), module (M), cell string (CS), or cell (C) level. The 1 MB (1)(1′) and associated hardware can be configured to operate under the maximum voltage across the series string of cells (CS_(s)). In particular embodiments, a load (7) can be electrically connected to the cells (C) to provide power to the load (7).

Method of Triggering iRIS Measurement. Now with primary reference to FIG. 7, which provides a block flow diagram of an illustrative method of triggering an impedance measurement (14) using the switching algorithm (79). The method can include setting the switching network (8) to measure a pack (P), module (M) or all, a portion of, or one of the individual cells (C) (block M1). The method can further include setting the impedance measurement trigger conditions (71) under which the IMD (1) will trigger a measurement of the pack (P), module (M) or individual cells (C) (block M2). Examples of trigger conditions (71), include, but are not necessarily limited to, time-based triggers (example, once per hour), trigger that are responsive to changes in pack, module or cell condition (example, voltage jump to a load condition or rest condition), or a combination of both time and system response. The method can further include monitoring the pack, module, or cell for occurrence of trigger conditions to initiate an IMD (1)(1′) impedance measurement (1) (block M3). The method can further include monitoring the pack (P), module (M) or cell (C) to determine whether or not the IMD (1)(1′) impedance measurement (14) should be performed upon occurrence of controlled conditions (4 c) (block M4). Controlled conditions (4 c) can include, as illustrative examples, an extended rest period (example, a parked car) with the system at electrochemical and/or thermal equilibrium, or during charge conditions (4 d) of the pack (P), module (M), or cell (C), or the charge algorithm of the pack (P), module (M) or cell (C) could be periodically paused for impedance measurements (14) to allow the pack (P), module (M) or cells (C) suitable time to allow voltages to equilibrate. Alternatively, impedance measurements (14) could wait for a particular charge load based on SOC (4 d), or the like. Upon determination of performing the impedance measurement (14) under controlled impedance measurement conditions (4 c) or uncontrolled conditions, the method can further include, setting the impedance measurement parameters (31) to include one or more of high-fidelity (14 a), mid-fidelity (14 b) or low-fidelity (14 c), number of frequencies (13) within the range, stimulus (10) level, load (7) detection, or the like (blocks M5 and M6). The method can further include triggering impedance measurement (14) of the pack (P), module (M) or cell (C) for the selected switch (S) settings and impedance measurement parameters (31) (blocks M7 and M8). In particular embodiments, the method can include triggering impedance measurement (14) under controlled impedance measurement conditions (4 c) at high-fidelity impedance measurement (14 a) which may include longer measurement durations (such as 80 sec), lower frequency measurements, and/or a higher number of frequencies within the measurement window for enhanced analytics and point-of-reference measurements (block M9). In particular embodiments, the method can further include triggering impedance measurements (14) under uncontrolled conditions at mid-fidelity impedance measurements (14 b) of relatively shorter measurement durations (such as 10 sec), and/or fewer number of frequencies (13) within the measurement window (block M10). Reasonably lower frequency measurements may be possible to ensure that the IMD (1)(1′) fully captures the charge transfer resistance (R_(ct)), but not so low that the measurement takes too long. The method can further include detecting an anomalous condition (64) in the impedance measurement time record (29) of the impedance measurement (14) (block M11). Each measurement conducted by the IMD (1) can, but need not necessarily, be associated with or combined with BMS (53) analytics such as voltage (V), current (I), temperature (T), or analytics derivable from any other sensor. If, based on the impedance measurement (14) and BMS (53) system analytics, an anomalous condition (64) is detected, the method can further include setting the switching network (8) to perform a series of low-fidelity impedance measurements (14 c) at the pack (P), module (M) and cell (C) level (block M12), and can further include in various combinations, adjusting the impedance measurement parameters (block M13) and performing impedance measurements (14) of the pack, module or cell, typically at low-fidelity (block M14), and if an anomalous condition (64) is validated is detected, warning of the anomalous condition (block M15).

Method of Assessing Battery State of Health in a Pack or Module. Now, with primary reference to FIG. 8, which provides a block flow diagram of an illustrative method of performing an impedance measurement (14) of a pack (P), module (M) or cell (C) using the switching algorithm (70). The method can include determining if the battery is in use (block N1). As illustrative examples, the method can determine if there a load (7) placed on the battery (4), under a controlled charge or an extended charge. In particular embodiments, the method can include pause steps coordinated with the charge algorithm. The method can further include setting switches (S) in the switch network (8) as needed for impedance measurement (14) of the pack (P), module (M) or cell (C) (block N2). Depending on requirements, the switch network (8) can be set a plurality of times for impedance acquisitions to enable impedance measurements of the pack (P), module (M), cell (C) or other sub-system level. The method can further include triggering impedance measurements (14) under controlled conditions such as SOC, temperature, which may not need to be real-time impedance measurements (14) (block N3). If under a charge condition, iRIS measurement can be taken at a plurality of different SOC conditions (4 c) under controlled conditions. In particular embodiments, the method can further include triggering impedance measurement (14) while the pack (P), module (M) or cell (C) is in use. If the pack (P), module (M) or cell (C) is under active use, or even during periodic rest intervals during active use (such as not under a controlled charge), trigger near real-time impedance measurements (14) for in-situ battery (4) assessment. In particular embodiments remote triggering can be performed if/when needed based on OEM (or other) determination (such as, performance metrics based on fleet data) (block N4). The method can further include assessing battery analytics to determine SOH (4 e), RUL, or stability (for example, instability due to cyber attack), which in particular embodiments can be combined with one or more BMS (53) analytics as needed (such as, battery power assessment, battery power management, battery capacity or battery energy fade) or combined with V, T, I sensor data for in-situ assessments (block N5). The method can further include detecting an anomalous condition (64) relating to pack, module or cell performance, stability, charge (block N6). In the event of a detected anomalous condition (64), the method can further include triggering near real time impedance measurements (14) (block N7). The method can further include confirming whether anomalous condition (65) comprises a repeatable deviant condition (65). (block N8). In the event of a non-repeatable anomalous condition (64) the system can return to normal assessment mode (block N1). In the event of a repeatable deviant condition (65), the method can further include generating a warning of the deviant condition (65) (block N9). For example, the OEM could be notified with a wireless warning indicator (68), the device, object, or vehicle (54) operator could be notified with a warning indicator (68), such as illumination of a warning light, and the BMS (53) could receive a warning that initiates appropriate controls on battery operations (such as, shutdown battery use, limit battery power consumption). The method can further include determining the source of the deviant condition (65) (blocks N10). For example, the battery system could initiate a series of switch (S) settings of the switch network (8) to isolate the specific pack (P), module (M), cell string (CS), or individual cells (C) (block N11). The method can further include triggering near real-time impedance measurements (14) of isolated pack (P), module (M), cell string (CS), or individual cell (C) (block N12). The method can further include analysis of impedance measurements (14) by comparison to pre-determined impedance measurement threshold value(s) (63) or pre-determined impedance measurement change rate threshold value(s) (67), or combinations thereof, to determine the source pack (P), module (M), or cell (C) associated with the deviant condition (65) (block N13). Upon determination of the source pack (P), module (M) or cell (C) which is the source of the deviant condition (65) (block N14), the method can further include triggering action to ensure safety of the object, device or vehicle (54) or the user (block N15).

Example I Three Cell Series String Impedance Measurement.

FIG. 9A includes battery impedance plots (16) of real impedance (18) on the X axis versus imaginary impedance (17) on the Y axis obtained by performing a plurality of impedance measurements (14) of three cells electrically interconnected in series cell string (CS_(s)) at high-fidelity impedance measurement (14 a) and at a mid-fidelity impedance measurement (14 b)(as shown in the illustrative example of FIG. 3B). High-fidelity impedance measurements (14 a) were conducted under normal conditions, without cell anomalous or deviant condition(s) (64)(65), under controlled conditions (4 c) (Controlled Measurement A and Controlled Measurement B). In this case, the impedance measurement parameters (31) included a start frequency (50) of 0.0125 Hz and a stop frequency (51) of 1638.4 Hz with eighteen total frequencies included in the impedance measurement (14) of 80 sec. The HCSD analysis algorithm was to generate the impedance spectra (15). As shown by the battery impedance plots (16), during batter use over a period of time, the impedance spectra (15) for Controlled Measurement B has shifted to the right of Controlled Measurement A due to aging of the three cells electrically connected in series (CS_(s)). Additionally, during the period in which the three cells electrically connected in series (CS_(s)) was in use In-Use Measurements (“IUM”) at mid-fidelity (14 b) were conducted to assess aging and stability of the three cells electrically interconnected in series (CS_(s)). In-Use Measurements can be conducted under load conditions (7 a) or no-load conditions (7 b) depending on the setting for the impedance measurement trigger conditions (71). In the example of FIG. 9A, the impedance measurement parameters (31) included HDHCSD with a start frequency (50) of 0.1 Hz up to a stop frequency (51) of 409.6 Hz with 24 total frequencies included in a 10 sec impedance measurement (14). As shown by the In-Use Measurements, impedance of the three cells increases causing a shift to the right between In-Use Measurement impedance plots (IUM 1, IUM 2, IUM 3) during use of the three-cell series string (CS_(s)) and generally comports with the expected increase in impedance between Controlled Measurement A and Controlled Measurement B.

Example II Three Cell Series String Impedance Measurement—Anomaly Detection.

FIG. 9B includes battery impedance plots (16) of a high-fidelity impedance measurement (14 a)(Controlled Measurement B) across the series string of three cells (CS_(s)) as shown in FIG. 9A, and a subsequent mid-fidelity impedance measurement (14 b) (In-Use Measurement 4 (IUM 4)) of the series string of three cells (CS_(s)) indicative of an anomalous condition (64) by the substantial comparative increase in the impedance of the series string of three cells (CS_(s)). This apparent deviation can be the basis for resetting impedance measurement parameters (31) and performance of a plurality of rapid low-fidelity impedance measurements (14 c) and further determination if the anomalous condition (64) is a repeatable impedance measurement (65) indicating a deviation condition (65) relating to failure of the SOH (4 e) or stability of the series string of three cells (CS_(s)).

Example III Three Cell Series String Impedance Measurement—Anamoly Condition.

FIG. 9C includes battery impedance plots (16) of a high-fidelity impedance measurement (14 a) (Controlled Measurement B) across the series string of three cells (CS_(s)) and IUM 4 as shown in FIG. 9B, and a subsequent plurality of low-fidelity impedance measurements (14 c) (Rapid Verification Measurements 1 and 2 (RVM 1 and RVM 2)) of the series string of three cells (CS_(s)) indicative of non-repeatable anomaly condition (64) (IUM 4). After In-Use Measurement 4, a series of low-fidelity impedance measurements (14 c)(RVM 1 and RVM 2) were triggered. In this example, the impedance measurement parameters (31) were HDHCSD with a start frequency (50) of 0.8 Hz and a stop frequency (51) of 409.6 Hz with 18 total frequencies included in the impedance measurement (14) over 1.2 sec. As shown in this example, the RVM 1 and RVM 2 shift to the left and approach the Controlled Measurement B indicating that In-Use Measurement 4 was a non-repeatable anomalous condition (64). Anomalous conditions (64) can be result from any one or a combination of sources including noisy data acquisition, interrupted impedance measurement, measurements during a transition from rest (7 b) to load (7 a) (or load to rest or change in load) of the series three cell string.

Example IV Three Cell Series String Impedance Measuremant—Deviation Verification.

FIG. 9D includes battery impedance plots (16) of a high-fidelity impedance measurement (14 a)(Controlled Measurement B) across the series string of three cells (CS_(s)) and IUM 4 as shown in FIG. 9C, and a subsequent plurality of low-fidelity impedance measurements (14 c) (Rapid Verification Measurements (RVM 3 and RVM 4)) of the series string of three cells indicative of a impedance measurement IUM 4. After In-Use Measurement 4, a series of low-fidelity impedance measurements (14 c)(RVM 3 and RVM 4) were triggered. In this example, the impedance measurement parameters (31) are HDHCSD with a start frequency (50) of 0.8 Hz and a stop frequency (51) of 409.6 Hz with 18 total frequencies included in the impedance measurement (14) over 1.2 sec. As shown in this example, the RVM 3 and RVM 4 shift to the right and away from IUM 4 indicating that In-Use Measurement 4 was a repeatable deviation in the impedance measurement (14). These data indicate a need to drill-down by adjusting switch network (8) settings) to identify the problematic cell (C). While this example is of a series three-cell string (CS_(s)), a drill-down on a greater number of cells can be conducted by subsequent adjusting the switch network (8) and additional impedance measurements (14).

Example V Three Cell Series String Impedance Measurement—Failure Detection.

FIG. 9E includes battery impedance plots (16) of low-fidelity impedance measurement (14 c) Rapid Failure Detection Measurements of each of Cell 1 (RFDM 1), Cell 2 (RFDM 2), and Cell 3 (RFDM 3) of the series string of three cells (CS_(s)) indicative of failure of Cell 2 in the series string of three cells (CS_(s)). Once a repeatable deviant condition (65) has been confirmed as shown in the example of FIG. 9D, the switch network (8) can be adjusted to serially perform low-fidelity impedance measurements (14 c) of Cell 1, Cell 2, and Cell 3 within the three-cell series string (CS_(s)). While this example was conducted under no-load conditions (7 b) of the three-cell series string, it can also be conducted under load conditions (7 a). Impedance measurements (14) were conducted using the low-fidelity impedance measurement (14 c) settings as used in the example of FIG. 9D. As shown in the impedance plots of Cells 1-3, Cell 2 has a significantly different impedance spectrum (15) as compared to Cell 1 and Cell 3. Cell 2 has failed. Once identified, appropriate warning indicators (68) can be generated and further IMD (1)(1′) measurements or analytics initiated to determine if the failure is related to SOH (4 e) cell stability, or other identifiable condition.

Example VI Four Cell Parallel String Impedance Measurement.

FIG. 10A includes battery impedance plots (16) of real impedance (18) on the X axis versus imaginary impedance (17) on the Y axis obtained by performing a plurality of impedance measurements of four cells electrically interconnected in parallel (CS_(p)) at high-fidelity (14 a) and at mid-fidelity (14 b)(as shown in the illustrative example of FIG. 3B). High-fidelity impedance measurements (14 a) were conducted under normal conditions, without cell anomalies, under controlled conditions (Controlled Measurement A and Controlled Measurement B). In this case, the impedance measurement parameters (31) included a start frequency (50) of 0.0125 Hz and a stop frequency (51) of 1638.4 Hz with eighteen total frequencies included in the impedance measurement (14) of 80 sec. HCSD analysis algorithm was used to determine the impedance spectra (15). As shown by the battery impedance plots (16), during use over a period of time, the impedance spectra (15) for Controlled Measurement B has shifted to the right of Controlled Measurement A due to aging of the four cells electrically connected in parallel (CS_(p)). Additionally, during the period in which the four cells electrically connected in parallel (CS_(p)) was in use In-Use Measurements (“IUM”) at mid-fidelity (14 b) were conducted to assess aging and stability of the four cells electrically interconnected in parallel (CS_(p)). In-Use Measurements can be conducted under load (7) or no-load conditions depending on the impedance measurement trigger conditions (71). In the example of FIG. 10A, the impedance measurement parameters (31) included HDHCSD with a start frequency (50) of 0.1 Hz and a stop frequency (51) of 409.6 Hz with 24 total frequencies included in a 10 sec impedance measurement (14). As shown by the In-Use Measurements, impedance of the parallel four cell string (CS_(p)) increases causing a shift to the right between In-Use Measurement impedance plots (IUM 1, IUM 2, IUM 3) during use of the parallel four cell string (CS_(p)) and generally comports with the expected increase in impedance between Controlled Measurement A and Controlled Measurement B.

Example VII Four Cell Parallel String Impedance Measurement—Anomaly Detection.

FIG. 10B includes battery impedance plots (16) of a high-fidelity impedance measurement (14 a) Controlled Measurement B across the parallel string of four cells (CS_(p)) as shown in FIG. 10A, and subsequent mid-fidelity impedance measurement (14 b) In-Use Measurement 4 (IUM 4) of the parallel string of four cells (CS_(p)) indicative of an anomalous impedance measurement condition (64) by the substantial comparative increase in the impedance of the parallel string of four cells (CS_(p)). This apparent anomalous condition (64) can be the basis for resetting impedance measurement parameters (31) and performance of a plurality of rapid low-fidelity impedance measurements (14 c) and further determination if the anomaly condition (64) is a non-repeatable anomaly or a repeatable deviant condition (65) relating to failure of the SOH (4 e) of the parallel string of four cells.

Example VIII Four Cell Parallel String Impedance Measurement—Anomaly Verification.

FIG. 10C includes battery impedance plots (16) of a high-fidelity impedance measurement (14 a) Controlled Measurement B across the parallel string of three cells and IUM 4 as shown in FIG. 10B, and a subsequent plurality of low-fidelity impedance measurements (14 c) Rapid Verification Measurements (RVM 1 and RVM 2) of the parallel string of four cells (CS_(p)) indicative of a non-repeatable anomaly condition (64) IUM 4. After In-Use Measurement 4, a series of low-fidelity impedance measurements (14 c) RVM 1 and RVM 2 were triggered. In this example, the impedance measurement parameters (31) were HDHCSD with a start frequency (5)) of 0.8 Hz and a stop frequency (51) of 409.6 Hz with 18 total frequencies included in the impedance measurement (14) over 1.2 sec. As shown in this example, the RVM 1 and RVM 2 shift to the left and approach the Controlled Measurement B indicating that In-Use Measurement 4 was non-repeatable anomaly condition (64). Anomalous conditions (64) can be from any one or a combination of sources including noisy data acquisition, interrupted impedance measurement (14), impedance measurements (14) during a transition from rest to load (7) (or load to rest or change in load) of the parallel four cell string (CS_(p)).

Example IX Four Cell Parallel String Impedance Measurement—Deviation Verification.

FIG. 10D includes battery impedance plots (16) of a high-fidelity impedance measurement (14 a) Controlled Measurement B across the parallel string of four cells (CS_(p)) and IUM 4 as shown in FIG. 10C, and a subsequent plurality of low-fidelity impedance measurements (14 c) Rapid Verification Measurements (RVM 3 and RVM 4) of the parallel string of four cells (CS_(p)). After In-Use Measurement 4, a series of low-fidelity impedance measurements RVM 3 and RVM 4 were triggered. In this example, the settings are HDHCSD with a starting frequency of 0.8 Hz up to 409.6 Hz with 18 total frequencies included in the measurement over 1.2 seconds. As shown in this example, the RVM 3 and RVM 4 shift to the right and away from IUM 4 indicating that In-Use Measurement 4 was repeatable impedance measurement (14) indicating a deviation condition (65). These impedance measurements (14) indicate a need to drill-down by adjustment of the switch network (8) to identify the cell (C) that is the source of the deviant condition (65) provided that the load can tolerate lower current with isolated cells, or a cell balancing scheme is not active. While this example is of a parallel four cell string (CS_(p)), a drill-down on a greater number of cells (C) can be conducted by subsequent adjusting the switch network (8) and additional impedance measurements (14).

Example X Four Cell Parallel String Impedance Measurement—Failure Detection.

FIG. 10E includes battery impedance plots (16) of low-fidelity impedance measurements (14 c) Rapid Failure Detection Measurements of each of Cell 1 (RFDM 1), Cell 2 (RFDM 2), Cell 3 (RFDM 3) and Cell 4 (RFDM 4) of the parallel string of fours cells (CS_(p)) indicative of failure of Cell 1 in the parallel string of four cells (CS_(p)). Once the deviant condition (65) has been confirmed as shown in the example of FIG. 10D, the switch network (8) can be serially adjusted to conduct low-fidelity impedance measurements (14 c) and individually measure impedance of Cell 1, Cell 2, Cell 3, and Cell 4 within the four-cell parallel string (CS_(p)). While this example was conducted under no-load conditions (7 a) of the four-cell parallel string (CS_(p)), it can also be conducted under load conditions (7 b). IMD (1)(1′) measurements were conducted using the low-fidelity measurement parameters (14 b) as used in the example of FIG. 10D. As shown in the impedance plots (16) of Cells 1-4, Cell 1 has a significantly different impedance spectrum (15) as compared to Cell 2, Cell3 and Cell 4. Cell 1 has failed. Once identified, appropriate warning indicators (68) can be generated and further impedance measurements (14) or analytics initiated to determine if the failure is related to SOH (4 e) or related to cell stability.

Example XI Impedance Measurement of a Cell Under Load Conditions and Under No-Load Conditions at 0.1 Hz.

FIG. 11A includes battery impedance plots (16) of mid-fidelity impedance measurements of a cell under load conditions (7 a)(as shown in the example of FIG. 3) and under no load conditions (7 b). As above described, the switching network (8) can be set to conduct impedance measurements under no-load (7 b) or load conditions (7 a) for advanced battery analytics, diagnostics and prognostics. In this example, two impedance measurements (14) (ULM1 and ULM2) of a cell (C) under load conditions (7 a) were conducted with a start frequency (50) of 0.1 Hz for 10 sec and two impedance measurements (14) (NLM1 and NLM2) were conducted under no load conditions (7 b) with a start frequency (50) of 0.1 Hz for 10 sec. These single-cell impedance measurements (14) were conducted when the cell (C) was being discharged from 3.67 V to 3.3 V (the measurement at 3.546 V was after the discharge to 3.3 V and subsequent rest where the voltage recovered). The impedance plots (16) evidence that the impedance measurements (16) of the cell (C) under load conditions (7 a) and under no-load conditions (7 b) are similar, but there are greater low-frequency effects under load due to the different rate of diffusion under load conditions.

Example XII Impedance Measurement of a Cell Under Load Conditions and Under No-Load Conditions at 0.3 Hz.

FIG. 11B includes battery impedance plots (16) of low-fidelity impedance measurements (14 c) of a cell (C) under load conditions (7 a) and under no load conditions (7 b). As above described, the switch network (8) can be set to conduct impedance measurements (14) under no-load or load conditions (7 a) (7 b) for advanced battery analytics, diagnostics and prognostics. In this example, two impedance measurements (14) (ULM1 and ULM2) of a cell (C) under load conditions (7 a) were conducted with a start frequency (50) of 0.3 Hz for 3.3 sec and two impedance measurements (14) (NLM1 and NLM2) were conducted under no load conditions (7 b) with a start frequency (50) of 0.3 Hz for 3.3 sec. These single-cell impedance measurements (14) were conducted when the cell (C) was being discharged from 3.67 V to 3.3 V (the measurement at 3.546 V was after the discharge to 3.3 V and subsequent rest where the voltage recovered). The impedance plots (16) evidence that the impedance measurements (16) of the cell (C) under load conditions (7 a) and under no-load conditions (7 b) are similar, but there are greater low-frequency effects under load due to the different rate of diffusion under load conditions.

Example XIII Impedance Measurement of a Cell Under Load Conditions and Under No-Load Conditions at 0.8 Hz.

FIG. 11C includes battery impedance plots (16) of low-fidelity impedance measurements (14 c) of a cell (C) under load conditions (7 a) and under no load conditions (7 b). As above described, the switch network (8) can be set to conduct impedance measurements (14) under no-load conditions (7 b) or load conditions (7 a) for advanced battery analytics, diagnostics and prognostics. In this example, two under impedance measurements (14) (ULM1 and ULM2) of a cell (C) under load conditions (7 a) were conducted with a start frequency (50) of 0.8 Hz for 1.2 seconds and two impedance measurements (NLM1 and NLM2) were conducted under no load conditions (7 b) with a start frequency (50) of 0.8 Hz for 1.2 seconds. These single-cell impedance measurements (14) were conducted when the cell (c) was being discharged from 3.67 V to 3.3 V (the measurement at 3.546 V was after the discharge to 3.3 V and subsequent rest where the voltage recovered). The impedance plots (16) evidence that the impedance measurements (14) of the cell (C) under load conditions (7 a) and under no-load conditions (7 b) are similar, but there are greater low-frequency effects under load due to the different rate of diffusion under load conditions.

Example XIV Impedance Measurement of a Four Cell Series String Under Load Conditions and Under No-Load Conditions at 0.1 Hz.

FIG. 12A is a battery impedance plot (16) of mid-fidelity impedance measurements (14) of four cells electrically connected in series (CS_(s)) under load conditions (7 a) and under no load conditions (7 b). In this example, two impedance measurements (ULM1 and ULM2) of a cell (C) were conducted under load conditions (7 a) with a start frequency (50) of 0.1 Hz for 10 sec and two impedance measurements (14) (NLM1 and NLM2) were conducted under no load conditions (7 b) with a start frequency (50) of 0.1 Hz for 10 sec. In this example, the four cell series string (CS_(s)), has one cell within the string subjected to a discharge condition to simulate, for example, a soft short condition if the four cell series string (CS_(s)) was under no load conditions (7 b). With only one cell (C) subjected to a load condition (7 a), the four-cell string (Cs) still clearly shows a change in the low-frequency tail which can be used an indicator to trigger low-fidelity impedance measurements (14 c). Otherwise, the impedance spectra (15) are very similar for the ohmic and charge transfer resistances. If there is no load condition (7 b), but the low-frequency Warburg tail droops, indicating the presence of a load (7), that can be an indication of a soft short condition which can trigger rapid low-fidelity impedance measurements. (14 c)

As can be easily understood from the foregoing, the basic concepts of the present invention may be embodied in a variety of ways. The invention involves numerous and varied embodiments of an IMD configured to perform in-line rapid impedance spectroscopy to provide rapid, broadband impedance measurements of battery packs, modules or cells using targeted frequency ranges under the operation of a switch network and switching algorithm to rapidly identify the source of anomalous impedance measurements which indicates failing or failure of one or more cells in a pack or module and methods for making and using such IMD, switch networks and switching algorithms including the best mode.

As such, the particular embodiments or elements of the invention disclosed by the description or shown in the figures or tables accompanying this application are not intended to be limiting, but rather illustrative of the numerous and varied embodiments generically encompassed by the invention or equivalents encompassed with respect to any particular element thereof. In addition, the specific description of a single embodiment or element of the invention may not explicitly describe all embodiments or elements possible; many alternatives are implicitly disclosed by the description and figures.

It should be understood that each element of an apparatus or each step of a method may be described by an apparatus term or method term. Such terms can be substituted where desired to make explicit the implicitly broad coverage to which this invention is entitled. As but one example, it should be understood that all steps of a method may be disclosed as an action, a means for taking that action, or as an element which causes that action. Similarly, each element of an apparatus may be disclosed as the physical element or the action which that physical element facilitates. As but one example, the disclosure of a “impedance measure” should be understood to encompass disclosure of the act of “impedance measuring”—whether explicitly discussed or not—and, conversely, were there effectively disclosure of the act of “impedance measuring”, such a disclosure should be understood to encompass disclosure of a “impedance measure” and even a “means for impedance measuring.” Such alternative terms for each element or step are to be understood to be explicitly included in the description.

In addition, as to each term used it should be understood that unless its utilization in this application is inconsistent with such interpretation, common dictionary definitions should be understood to be included in the description for each term as contained in Merriam-Webster's Collegiate Dictionary, each definition hereby incorporated by reference.

All numeric values herein are assumed to be modified by the term “about”, whether or not explicitly indicated. For the purposes of the present invention, ranges may be expressed as from “about” one particular value to “about” another particular value. When such a range is expressed, another embodiment includes from the one particular value to the other particular value. The recitation of numerical ranges by endpoints includes all the numeric values subsumed within that range. A numerical range of one to five includes for example the numeric values 1, 1.5, 2, 2.75, 3, 3.80, 4, 5, and so forth. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint. When a value is expressed as an approximation by use of the antecedent “about,” it will be understood that the particular value forms another embodiment. The term “about” generally refers to a range of numeric values that one of skill in the art would consider equivalent to the recited numeric value or having the same function or result. Similarly, the antecedent “substantially” means largely, but not wholly, the same form, manner or degree and the particular element will have a range of configurations as a person of ordinary skill in the art would consider as having the same function or result. When a particular element is expressed as an approximation by use of the antecedent “substantially,” it will be understood that the particular element forms another embodiment.

Moreover, for the purposes of the present invention, the term “a” or “an” entity refers to one or more of that entity unless otherwise limited. As such, the terms “a” or “an”, “one or more” and “at least one” can be used interchangeably herein.

Thus, the applicant(s) should be understood to claim at least: i) each of the IMD, switch networks, and switching algorithms herein disclosed and described, ii) the related methods disclosed and described, iii) similar, equivalent, and even implicit variations of each of these devices and methods, iv) those alternative embodiments which accomplish each of the functions shown, disclosed, or described, v) those alternative designs and methods which accomplish each of the functions shown as are implicit to accomplish that which is disclosed and described, vi) each feature, component, and step shown as separate and independent inventions, vii) the applications enhanced by the various systems or components disclosed, viii) the resulting products produced by such systems or components, ix) methods and apparatuses substantially as described hereinbefore and with reference to any of the accompanying examples, x) the various combinations and permutations of each of the previous elements disclosed.

The background section of this patent application provides a statement of the field of endeavor to which the invention pertains. This section may also incorporate or contain paraphrasing of certain United States patents, patent applications, publications, or subject matter of the claimed invention useful in relating information, problems, or concerns about the state of technology to which the invention is drawn toward. It is not intended that any United States patent, patent application, publication, statement or other information cited or incorporated herein be interpreted, construed or deemed to be admitted as prior art with respect to the invention.

The claims set forth in this specification, if any, are hereby incorporated by reference as part of this description of the invention, and the applicant expressly reserves the right to use all of or a portion of such incorporated content of such claims as additional description to support any of or all of the claims or any element or component thereof, and the applicant further expressly reserves the right to move any portion of or all of the incorporated content of such claims or any element or component thereof from the description into the claims or vice-versa as necessary to define the matter for which protection is sought by this application or by any subsequent application or continuation, division, or continuation-in-part application thereof, or to obtain any benefit of, reduction in fees pursuant to, or to comply with the patent laws, rules, or regulations of any country or treaty, and such content incorporated by reference shall survive during the entire pendency of this application including any subsequent continuation, division, or continuation-in-part application thereof or any reissue or extension thereon.

Additionally, the claims set forth in this specification, if any, are further intended to describe the metes and bounds of a limited number of the preferred embodiments of the invention and are not to be construed as the broadest embodiment of the invention or a complete listing of embodiments of the invention that may be claimed. The applicant does not waive any right to develop further claims based upon the description set forth above as a part of any continuation, division, or continuation-in-part, or similar application. 

1. A device, comprising: a processor communicative coupled to a non-transitory computer readable media containing a switching algorithm; an impedance measurement device; and a switching circuit controlled by said switching algorithm under control of said processor to connect a plurality of cells to said impedance measurement device, said switching circuit switchable to electrically connect said plurality of cells (C1, C2, . . . C_(n)) in a series string of cells (C1 s, C2 s, . . . C_(ns)), or electrically connect said plurality of cells (C1, C2, . . . C_(n)) in a parallel string of cells (C1 p, C2 p, . . . C_(np)), or electrically connect all of said plurality of cells (C1, C2, . . . C_(n)) interconnected in a series string of cells (s) and/or in a parallel string of cells (p). 